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UG-040
You can now open the Automated Register Window Builder
application and load the file for the part onto your evaluation
board.
POWERING THE BOARD
The AD1937/AD1939 evaluation board requires power supply
input of ±12 V dc and ground to the three binding posts; +12 V
draws ~250 mA, and ?12 V draws ~100 mA. The on-board
regulators provide two 3.3 V rails and one 5.0 V rail. The 3.3 V
rails supply AVDD and DVDD for the AD1937/AD1939 ; DVDD
also supplies power for the peripheral active components on the
board. The 5.0 V rail provides voltage only to the AD1937/
AD1939 internal regulator, which consists of a PNP pass tran-
sistor and a few passive components. The PNP is driven into
3.3 V regulation by the VDRIVE pin of the AD1937/AD1939,
with the VSUPPLY and VSENSE pins acting as power and
feedback for the regulator. An appropriate sized PNP can supply
3.3 V to the AVDD and DVDD pins of the AD1937/AD1939.
The jumper blocks are shown in Figure 6 and Figure 7.
EvaluationBoardUserGuide
SETTING UP THE MASTER CLOCK (MCLK)
The AD1937/AD1939 evaluation board has a series of jumpers
that give the user great flexibility in the MCLK clock source of
the AD1937/AD1939. MCLK can come from six different
sources: passive crystal, active oscillator, external clock in, S/PDIF
receiver, and two header connections. Note that the complex
programmable logic device (CPLD) on the board must have a
valid clock source; the frequency is not critical. These jumper
blocks can assign a clock to the CPLD as well. Most applications
of the board use MCLK from either the S/PDIF receiver or one
of the header (HDR) inputs. Figure 8 to Figure 10 show the on-
board active oscillator disabled so that it does not interfere with
the selected clock. The clock feed to the CPLD comes directly
from the clock source.
Note that, if the HDR connectors are to be driven with MCLK
from a source on the evaluation board, SW2 and/or SW3 must
be switched from the IN position to the OUT position.
193X_MCLKI
C96
Q1
L7
DISABLE
JP18
JP19
1938_MCLKI
R160 JP22
JP20 MCLKO C147
XTAL
U18
J22
R117
C158
JP23
CPLD
U21
Y1
R167
193X_MCLKO
JP25
OSC DISABLE HDR1
MAIN REGS
193X REG
C122
JP15
ENABLE
DISABLE
JP5 JP6 JP7
HDR2
JP27
JP28
EXT CLK
JP29
R174
R169
R172
U22
R175
J23
Figure 6. AD1939 Main Regulators Active
8416
JP30
C168
C170
EXT CLK IN
C96
Q1
HDR2
JP31
HDR1
Figure 8. S/PDIF Receiver as MCLK Master; the AD1939 and CPLD as Slaves
193X_MCLKI
DISABLE
R117
JP18
JP20 MCLKO C147
XTAL
J22
JP19
MAIN REGS
193X REG
C122
JP15
ENABLE
DISABLE
JP5 JP6 JP7
L7
C158
1938_MCLKI
R160 JP22
JP23
CPLD
U21
JP25
Y1
R167
U18
193X_MCLKO
OSC DISABLE HDR1
Figure 7. AD1939 Internal Regulator Active
The first step in using the AD1937/AD1939 internal regulator is
to provide power to the regulator circuit by moving the AD1937/
AD1939 REG jumper from DISABLE to ENABLE, as shown in
Figure 7. Three discrete jumpers allow the AD1937/AD1939 to
be run from either the main AVDD and DVDD regulators or
HDR2
JP27
JP28
EXT CLK
JP29
8416
JP30
HDR2
R169
R172
U22
R174
C168
C170
R175
J23
EXT CLK IN
the AD1937/AD1939 internal regulator. These jumpers also
allow measurement of current drawn by the individual sections
of the AD1937/AD1939. The only components on the AD1937/
JP31
HDR1
Figure 9. HDR1 as MCLK Master; the AD1939, CPLD, and HDR2 as Slaves
AD1939 side of the jumper are the AD1937/AD1939 and the
supply decoupling capacitors.
Rev. 0 | Page 4 of 32
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